Apparatus and method for fabricating semiconductor devices

ABSTRACT

Disclosed is apparatus and method for fabricating semiconductor devices, in particular comprising a wafer chuck for holding a semiconductor wafer on which a predetermined thin layer is deposited; a processing chamber for injecting etching gas toward the wafer to form a predetermined pattern; and a clamp or a shadow ring provided on an edge of the wafer being held by the wafer chuck and preventing the edge from being etched, and thereby forming a protective step around the edge. Therefore, during a subsequent CMP process, the pattern adjacent to the edge of the wafer can be prevented from being over-polished, and reliability as well as productivity of the semiconductor devices can be improved.

BACKGROUND OF THE INVENTION

1. Field of the invention

The present invention relates to an apparatus and method for fabricatingsemiconductor devices, and more particularly for forming a protectivestep which can prevent an edge of a semiconductor wafer from beingover-polished during a chemical-mechanical polishing (CMP) process.

2. Description of the Prior Art

In general, a CMP process has been applied as a planarization processfor insulation layers as well as a damascene process for metalliclayers.

The CMP process is employed in polishing a semiconductor wafer surfaceby using the friction between slurry and a pad, in which variousconsumables, such as slurry, a pad, a backing film, a diamondconditioner, etc., are used. The polishing property of this process isdependant upon pressure distribution between the pad and the wafer whilethe wafer is polished in close contact with the pad.

When the amount of polishing on one surface of a blanket wafer isuniformly maintained, pressure on the other surface of the wafer may becontrolled. When the amount of polishing on an edge of the wafer iscontrolled, pressure on a retainer ring on the circumference of the CMPequipment may be controlled. However, there is a problem in that it isdifficult to control the level of polishing resulting from a chiplayout, a pattern density, a pattern height and so forth.

Before such a CMP process is performed, the wafer undergoes depositionof various thin layers, and then a predetermined pattern is formed onthe wafer by photolithography and etching processes.

In the photolithography process, to inhibit photoresist contamination aswell as particle generation, the photoresist applied on the wafer, inparticular on the edge of the wafer, is subjected to rinsing.

The photolithography and etching processes will be specificallydescribed below with reference to attached drawings.

Referring to FIG. 1A, to form a pattern prior to the CMP process,various thin layers are deposited on the wafer 10, and then theresulting wafer is subjected to photolithography as well as etchingprocesses so as to form a predetermined pattern thereon.

Specifically, in the photolithography process, a predeterminedinsulation layer is deposited on the wafer 10, an anti-reflection layerand a photoresist layer are in turn applied on the insulation layer, anedge 12 of the wafer is rinsed, only photoresist on the edge 12 isremoved, the remnant photoresist is photosensed in the presence of amask, and a predetermined pattern 11 is formed by a reactive ion etching(RIE) process.

In general, in the RIE process, the wafer is wholly exposed to reactivegas, thereby a pattern area free from photoresist is etched togetherwith the edge 12 of the wafer from which photoresist was rinsed andremoved. Therefore, a height difference is formed in proportion to theetched amount.

In the CMP process after the thin layers are deposited on the pattern 11which is generated by the RIE process, the edge 12 from which a part ofphotoresist was rinsed and removed is over-polished, which incurs damageof the wafer 10 as shown in FIG. 1B.

To avoid this problem, a dummy chip has been used, but it acts as afactor which decreases the yield of semiconductor devices. In addition,when the photoresist is not rinsed, the edge of the wafer may be freefrom damage. However, the wafer may not only be contaminated by thenon-rinsed photoresist during transporting of the wafer. The edgethereof may be formed with particles.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made to solve theabove-mentioned problems occurring in the prior art, and an object ofthe present invention is to provide an apparatus for fabricatingsemiconductor devices, in which during an etching process an edge of asemiconductor wafer is constrained from being etched by using a clamp.

Another object of the present invention is to provide an apparatus forfabricating semiconductor devices, in which during an etching process anedge of a semiconductor wafer is constrained from being etched by usinga shadow ring.

Another additional object of the present invention is to provide amethod for fabricating semiconductor devices, in which during a CMPprocess after formation of a protective step on an edge of asemiconductor wafer, over-polishing, which results in a heightdifference between the edge and a pattern of the wafer, is prevented.

In order to accomplish these objects, according to one embodiment of thepresent invention, there is provided an apparatus for fabricatingsemiconductor devices, comprising: a wafer chuck for holding asemiconductor wafer on which various thin layers has been deposited; aprocessing chamber for injecting etching gas toward the wafer to form apredetermined pattern; and a clamp, attached to an edge of the waferbeing held by the wafer chuck, for preventing the edge from beingetched.

According to another embodiment of the present invention, there isprovided an apparatus for fabricating semiconductor devices, comprising:a wafer chuck for holding a semiconductor wafer on which various thinlayers has been deposited; a processing chamber for injecting etchinggas toward the wafer to form a predetermined pattern; and a shadow ring,provided in the chamber upwardly spaced apart from the wafer being heldby the wafer chuck, for preventing the edge from being etched.

According to another additional embodiment of the present invention,there is provided a method for fabricating semiconductor devices using asemiconductor wafer formed with various thin layers thereon, comprisingthe steps of: covering the thin layers with photoresist and thenpartially removing the photoresist from an edge of the wafer; etchingthe wafer except for the edge which is free from the photoresist withetching gas, so as to form a predetermined pattern; forming a protectivestep on the edge at the same time as the pattern is being formed; andperforming planarization of the wafer formed with the pattern and theprotective step.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more apparent from the following detailed descriptiontaken in conjunction with the accompanying drawings, in which:

FIGS. 1A and 1B illustrate the procedures for forming a semiconductordevice according to the prior art;

FIG. 2 is a cross-sectional view of a processing chamber for ion etchingin an apparatus for fabricating a semiconductor device according to onepreferred embodiment of the present invention;

FIG. 3 is a cross-sectional view of a processing chamber for ion etchingin an apparatus for fabricating a semiconductor device according toanother preferred embodiment of the present invention; and

FIGS. 4A and 4B illustrate the procedures for forming a semiconductordevice according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a preferred embodiment of the present invention will bedescribed with reference to the accompanying drawings. In the followingdescription and drawings, the same reference numerals are used todesignate the same or similar components, and so repetition of thedescription on the same or similar components will be omitted.

Referring to FIG. 2, in an apparatus for fabricating semiconductordevices, a processing chamber 100 used in an ion etching process ishoused with a wafer chuck 101 for holding a wafer 102, a gas injectionhead 103 for injecting gas toward the wafer 102, and a clamp 104 forgrasping the wafer 102 and preventing an edge of the wafer from beingetched.

The wafer 102 is subjected to deposition of various thin layers thereon,and then patterned in a predetermined pattern by a photolithographyprocess and an etching process.

In the photolithography process, to restrict photoresist contaminationand particle generation, the edge of the wafer 102 is rinsed, and onlythen is the photoresist on the edge removed.

The edge of the wafer 102 is grasped by the clamp 104, so that it is notetched during the etching process. As a result, the edge of the wafer isformed with a protective step.

In the CMP process following the etching process, a surface of the wafer102 is worked by slurry supplied from the exterior as well as frictionapplied from a pad, so that the wafer 102 has a different level ofpolishing resulting from a layout of the device, a pattern density, apattern thickness and so forth.

According to previous process in the art, during the CMP process afterdepositing various thin layers and forming the pattern, the edge of thewafer may be formed at a different height than the rest of the wafer.However, according to the process of the present invention, thisdifferent height can be prevented by provision of the protective step onthe edge.

Therefore, the protective step around the edge of the wafer makes itpossible to obtain planarization of the insulation layer deposited onthe pattern of the wafer 102 for the CMP process and to prevent the edgeof the wafer from being over-polished, and thus reliability andproductivity of the semiconductor device can be increased.

Referring to FIG. 3, a processing chamber 100 according to anotherembodiment of the present invention is housed with a wafer chuck 101 forholding a wafer 102, a gas injection head 103 for injecting gas towardthe wafer 102, and a shadow ring 105 for preventing an edge of the wafer102 from being etched.

The wafer 102 is subjected to deposition of various thin layers thereon,and then patterned in a predetermined pattern by a photolithographyprocess and an etching process.

In the photolithography process, to restrict photoresist contaminationand particle generation, the edge of the wafer 102 is rinsed, and onlythen is the photoresist on the edge removed.

The edge of the wafer 102 is prevented from being etched during theetching process by the shadow ring 105, so that it is formed with aprotective step.

In the CMP process following the etching process, a surface of the wafer102 is worked in cooperation with slurry supplied from the exterior aswell as friction applied from a pad, so that the wafer 102 has adifferent level of polishing resulting from a layout of the device, apattern density, a pattern thickness and so forth.

According to previous process in the art, during the CMP process afterdepositing various thin layers and forming the pattern, the edge of thewafer may be formed at a different height than the rest of the wafer.However, according to the process of the present invention, thisdifferent height can be prevented by provision of the protective step onthe edge.

Therefore, the protective step around the edge of the wafer makes itpossible to obtain planarization of the insulation layer deposited onthe pattern of the wafer 102 for the CMP process and to prevent the edgeof the wafer from being over-polished, and thus reliability andproductivity of the semiconductor device can be increased.

The procedures for processing the semiconductor device using theprocessing chamber as above-mentioned will be described with referenceto FIGS. 4A and 4B.

Referring to FIG. 4A, various thin layers is deposited on a wafer 200,and then a predetermined pattern 210 is formed with the resulting waferby using a photolithography process and an etching process. The layerdeposited on the wafer 200 is an insulation layer such as an oxide layeror a silicon nitride layer, or a conductive layer such as a titan layer,a titan nitride layer, a tungsten layer, an aluminum layer or a copperlayer.

In the photolithography for patterning the wafer, the top surface of thewafer with the deposited layer is covered with photoresist so as to formthe pattern 210. Only the photoresist applied on an edge of the wafer isremoved through rinsing so as to prevent the remnant photoresistcontamination and particle generation. Here, the rinsed edge has a widthof less than 3 millimeters.

The edge free from the photoresist is not exposed to etching gas due toa clamp 104 provided in the processing chamber. Therefore, the edgeprotected from the etching gas by means of the clamp 104 is providedwith a protective step 220 after completion of the etching process.

This protective step 220 gets rid of the height difference between thepattern 210 and the edge resulting from the CMP process which followsthe etching process, so that it can prevent the pattern 210 and the edgefrom being over-polished.

Up to now, one preferred embodiment of the present invention has beendescribed, for example, with respect to formation of the protective stepusing the clamp 104. Similarly, the shadow ring 105 is installed in theprocessing chamber 100 upwardly spaced apart from the wafer chuck 101,so that the edge of the wafer is protected from etching conditionsduring the etching process, thus forming the protective step 220. Withrespect to formation of the protective step 220, this configuration canalso obtain the same effects as the previous configuration.

FIG. 4 shows the wafer 200, which is formed with the protective step 220and the pattern 210 by the CMP process. This protective step 220 allowsthe pattern 210 and the edge to avoid being over-polished resulting fromthe height difference between the pattern 210 and the edge during theCMP process.

As seen from the above, in the pattern formation process prior to theplanarization process for fabricating semiconductor devices, to restrainthe edge of the wafer from being etched during the etching process, theedge is provided with the protective step through employment of theclamp or the shadow ring. Therefore, during the CMP process followingthe pattern formation process, the edge can be prevented from beingover-polished, and thus reliability as well as productivity of thesemiconductor devices can be increased.

Although a preferred embodiment of the present invention has beendescribed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

1. An apparatus for fabricating semiconductor devices, comprising: awafer chuck for holding a semiconductor wafer on which various thinlayers has been deposited; a processing chamber for injecting etchinggas toward the wafer to form a predetermined pattern; and a clamp,attached to an edge of the wafer being held by the wafer chuck, forpreventing the edge from being etched.
 2. An apparatus as claimed inclaim 1, wherein the clamp forms a protective step on the edge byconstraining the edge from being etched.
 3. An apparatus for fabricatingsemiconductor devices comprising: a wafer chuck for holding asemiconductor wafer on which various thin layers has been deposited; aprocessing chamber for injecting etching gas toward the wafer to form apredetermined pattern; and a shadow ring, provided in the chamberupwardly spaced apart from the wafer being held by the wafer chuck, forpreventing the edge from being etched.
 4. An apparatus as claimed inclaim 3, wherein the shadow ring forms a protective step on the edge byconstraining the edge from being etched.